Direct Digital Frequency Synthesis Using a Modified Cordic

This paper introduces a new approach to direct digital frequency synthesis (DDFS) based on the Coordinate Rotation (CORDIC) algorithm. The modifications to the standard CORDIC algorithm introduced in this paper allow fine frequency resolution, and exhibit significant potential for low power applications. The new architecture does not need a large ROM and can be implemented on a general purpose processor, or on a flexible ASIC architecture. 1 DIRECT DIGITAL FREQUENCY SYNTHESIS All passband communication systems employ some form of up/down conversion. Frequency conversion is required to transmit the data in the desired frequency band. Different frequency bands are also used to allow efficient use of the allocated spectrum when using FDMA. The baseband signal is up/down converted by either multiplication by a sinusoid of controllable frequency (e.g. QAM) or by directly modulating the frequency of the sinusoid (e.g. FM, GMSK) [1]. A fully digital implementation of any communication system requires direct digital frequency synthesis (DDFS) [1],[2] . Digital frequency synthesis is also preferred over the analog approach due to lower phase noise, fine frequency resolution and the ability to rapidly change frequency. Conventional methods for digital frequency synthesis use a phase accumulation technique, as shown in Figure 1. The phase control word, W, is continuously increased in constant increments of α. W is used as an argument to a sine lookup table or generator. Since frequency is defined as the derivative of the phase, the output of the sine generator is a sinusoid of a constant frequency, determined by α. This derivation is summarized in equation (1) [1],[2]. W Sin() Look Up or Generation + Reg α N bits Sin(W) Figure 1. Conventional frequency synthesis architecture clk N out N clk f t f W t t f t W 1 2 d d 2 1 ; 2 ) ( ; ) ( + = = = = α θ π π θ α (1) Most of the DDFS designs used today store pre-computed samples of a sinusoid in a ROM lookup table [2]. A major disadvantage of this approach is the requirement of a rather large ROM in order to achieve acceptable spectral purity. In traditional ROM based DDFS systems, the size of the ROM grows exponentially with spectral purity. An alternative method for generation of a sinusoid is based on trigonometric definition and properties of the sine and cosine. This method, known as coordinate rotation (CORDIC) [3],[6], requires very few constant coefficients and is more suitable for implementation in a flexible ASIC architecture or a general purpose processor. Two major problems have prevented use of the CORDIC algorithm in DDFS architectures, namely poor frequency resolution and potentially high power consumption. The architecture proposed in this paper introduces modifications to the classical CORDIC algorithm that circumvent both of these problems. 2 CONVENTIONAL CORDIC In the CORDIC algorithm [6], sine & cosine of the desired angle are calculated using a cascade of N ’sub-rotation’ stages. The k stage rotates the input complex number, considered as a 2 element vector (2-vector), by ±δ/2 (δ=π/2) radians depending on the k bit of W. By changing the phase control word we can rotate an initial vector by any angle in the range [0..π-δ/2] in increments of δ/2 radians. Each stage implements a Givens’ plane rotation, of the form:             Θ Θ − Θ =             Θ Θ Θ − Θ =       ′ ′ y x y x y x 1 tan tan 1 cos cos sin sin cos (2). CORDIC based designs recognize that the multiplications by cos(Θ) for all sub-rotation stages can be collected together into a single constant